clc; clear all
syms R1 s L2 C3 R4 L5 L6;
r=[1/R1 1/(s*L2) s*C3 1/R4 1/(s*L5) 1/(s*L6)] %电路各支路的导纳%
Yb=zeros(6,6);
syms Yb
for i=1:6
Yb(i,i)=r(1,i);
end
Y
clc; clear all
syms R1 s L2 C3 R4 L5 L6;
r=[1/R1 1/(s*L2) s*C3 1/R4 1/(s*L5) 1/(s*L6)] %电路各支路的导纳%
Yb=zeros(6,6);
syms Yb
for i=1:6
Yb(i,i)=r(1,i);
end
Y