我从没有见过第2种写法
请使用第一种用法,另外,写case的时候 千万要写 default,即使你条件写满了 也要写default,避免产生latch
coding rule 是很死的东西,要遵守,就像遵守法律一样
可参考 huawei coding rule
verilog case如case（{bit2,bit1,bit0})3'b001:begin.end3'b010:be
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