Comparator-based switched-capacitor pipelined analog-to-digital converter with comparator preset, and comparator delay compensation
基于校准器可开关电容管式数码模拟转换器,以及校准器预设和校准器延迟补偿仪（的前提下）
Carsten Wulff • Trond Ytterdal
Received: 13 March 2010 / Revised: 30 November 2010 / Accepted: 3 December 2010 / Published online: 19 December 2010
接收日期,2010年3月13日,最近修改 2010年11月30日,接受日期,2010年11月3日
2 The Author(s) 2010. This article is published with open access at Springerlink.com
本文公开发表于springerlink.com
Abstract 内容概要
We present a differential comparator-based
switched-capacitor (CBSC) pipelined analog-to-digital
converter (ADC) with comparator preset, and comparator
delay compensation.
我们演示了一款全新的基于校准器的,可开关电容管式数码模拟转换器,以及校准器预设和校准器补偿仪
Compensating for the comparator
delay by digitally adjusting the comparator threshold
improves the ADC resolution from 2.5-bit to 7.05-bit.
该校准器延迟补偿仪,通过数控调整校准器的临界值,把数码模拟转换器的解析度从2.5bit,提高到了7.05bit.
The ADC is manufactured in a 90 nm CMOS technology, with
a core area of 0.85 mm 9 0.35 mm, a 1.2 V supply for the
core and 1.8 V for the input switches.
这个ADC是通过90nm CMOS技术制造,核心区域为0.85毫米, 90.35毫米.
核心电源电压1.2V,开关输入电压1.8V.
It has an effective
number of bits (ENOB) of 7.05-bit, and a power dissipation
of 8.5 mW at 60 MS/s.
它的bits有效数量为7.05bit,它的能量损耗为8.5nw,当速度为60MS/秒的时候.
Keywords Analog-to-digital converter 2 Comparatorbased
switched-capacitor circuit
关键词,数码模拟转换器
校准器为基础的,
可开关电容电路
哈哈,我能理解的就大概这个意思了.