Question

Error (10500):VHDL syntax error at cqg.vhd(31) near text ":=

Answer 1

if d1:="1010" then d1:="0000";i1:=i1+"0001";应为if d1="1010" then d1:="0000";i1:=i1+"0001";

variable i1:std_logic_vector(3 downto 0);

variable d1:std_logic_vector(3 downto 0);应当在引用变量的进程中变量声明,不能再结构体中声明普通变量,除非是共享变量（SHARED VARIABLE）.而且变量也不能作为敏感参量放在进程的敏感信号表当中.